1. Technology Field
The invention generally relates to a data access method, and more particularly, to a data access method for accessing a rewritable non-volatile memory module through a plurality of thread modules and a memory controller and a memory storage apparatus using the same.
2. Description of Related Art
Along with the widespread of digital cameras, cell phones, and MP3 in recently years, the consumers' demand to storage media has increased drastically. Rewritable non-volatile memory is one of the most adaptable memories for portable electronic products (for example, notebook computers) due to its characteristics such as data non-volatility, low power consumption, small volume, non-mechanical structure, and high access speed. A solid state drive (SSD) is a storage apparatus which uses a flash memory as its storage medium. Thus, in recent years, the flash memory industry has become a major part of the electronic industry.
A rewritable non-volatile memory storage apparatus has a plurality of physical blocks, and each of the physical blocks has a plurality of physical pages. While writing data into a physical block, the data has to be written according to the sequence of the physical pages in the physical block. In addition, a physical page containing data should be erased before it is used for writing new data. In particular, because physical block is the smallest erasing unit and physical page is the smallest programming (writing) unit, physical blocks in a flash memory storage system are usually grouped into a data area and a spare area.
Physical blocks in the data area are used for storing data written by a host system. To be specific, the memory management circuit converts logical access addresses to be accessed by the host system into logical pages of logical blocks and maps the logical pages of the logical blocks to the physical pages of the physical blocks in the data area. Namely, in the management of a flash memory module, the physical blocks in the data area are considered physical blocks that have been used (for example, already contain data written by the host system). For example, the memory management circuit records the mapping relationship between the logical blocks and the physical blocks of the data area by using a logical block-physical block mapping table, wherein the logical pages in a logical block sequentially correspond to the physical pages in the physical block mapped to the logical block.
Physical blocks in the spare area are used for substituting the physical blocks in the data area. To be specific, as described above, a physical block already containing data has to be erased before it is used for writing new data, and the physical blocks in the spare area are designed for writing update data to replace the physical blocks originally mapped to the logical blocks. Accordingly, the physical blocks in the spare area are blank or available physical blocks (i.e., no data is recorded therein or data recorded therein is already marked as invalid data).
Since the physical blocks of the data area and the physical blocks of the spare area are alternatively used for storing data written by the host system, in order to allow the host system to smoothly access the physical blocks alternatively used for storing data, the rewritable non-volatile memory storage apparatus provides logical blocks and corresponds the logical access addresses to be accessed by the host system to the logical pages in these logical blocks. To be specific, the rewritable non-volatile memory storage apparatus converts the logical access addresses to be accessed by the host system into corresponding logical blocks and records and updates the mapping relationship between the logical blocks and the physical blocks of the data area in the logical block-physical block mapping table to reflect the alternation of the physical blocks. Thus, the host system simply accesses the logical access addresses while the flash memory storage system actually reads data from or writes data into the corresponding physical blocks according to the logical block-physical block mapping table.
To be specific, when the host system is about to store data into a logical access address, the control circuit of the flash memory storage system identifies the logical block corresponding to the logical access address, selects a physical block from the spare area, and writes the new data into the physical block selected from the spare area (also referred to as a child physical block) to replace the physical block originally mapped to the logical block (also referred to as a mother physical block). Herein the operation of mapping a logical block to a mother physical block and a child physical block is referred to as opening mother-child blocks. Thereafter, when the host system is about to write data into another logical block, the flash memory storage system has to perform a data merging procedure to merge the valid data that are stored in the mother physical block and the child physical block mapped to this logical block (i.e., merge the data belonging to the logical block into a single physical block).
For example, in the data merging procedure, the rewritable non-volatile memory storage apparatus copies valid data in the mother physical block to the child physical block and re-maps the logical block to the child physical block (i.e., associates the child physical block with the data area). In addition, the rewritable non-volatile memory storage apparatus erases the original mother physical block in the data area and links it to the spare area.
Along with the increase in the capacity of each logical block, the rewritable non-volatile memory storage apparatus needs to spend more time to perform aforementioned data merging procedure, so as to execute a next write command. In addition, when a single data bus is disposed in a memory storage apparatus for connecting the control circuit and the rewritable non-volatile memory module and a plurality of thread modules is disposed for accessing the rewritable non-volatile memory module, because these thread modules transmit data by sharing the single data bus, even more time is required for executing a write command. For example, if a background thread module for processing data accesses in a background mode is executing aforementioned data merging procedure to write data and a foreground thread module receives a write command from the host system, the foreground thread module has to wait until the background thread module finishes the data merging procedure before it starts to execute the write command. In particular, the foreground thread module may also need to execute a data merging procedure before executing the write command. Thus, the time required for executing the write command becomes too long and accordingly the foreground thread module cannot respond to the host system in time. As a result, a timeout problem is caused.
Nothing herein should be construed as an admission of knowledge in the prior art of any portion of the present invention. Furthermore, citation or identification of any document in this application is not an admission that such document is available as prior art to the present invention, or that any reference forms a part of the common general knowledge in the art.